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MV3506/7/8 1 ds3133-2.1 MV3506 mv3507 mv3508 a-law filter/codec m -law filter/codec these devices are silicon gate cmos companding encoder/decoder integrated circuits designed to implement the per channel voice frequency codecs used in pcm systems. they contain the band-limiting filters and the analog to digital conversion circuits that conform to the desired transfer characteristic. the MV3506 and mv3508 provide the european a-law companding and the mv3507 provides the north american m -law companding characteristic. the mv3508 has programmable squelch circuitry to reduce idle channel noise. these circuits provide the interface between the analog signals of the subscriber loop and digital signals of the pcm highway in a digital telephone switching system. the devices operate from dual power supplies of 5v. features n low power cmos 80mw (operating) 10mw (standby) n meets or exceeds at & t3, and ccitt g.711, g.712 and g.733 specifications n input analog filter eliminates need for external anti- aliasing prefilter n uncommitted input and output op. amps for programming gain n output op. amp provides 3.1v into a 1200 ohms load or can be switched off for reduced power (70mw) n encoder has dual-speed auto-zero loop for fast acquisition on power-up n low absolute group delay = 410 microseconds at 1 khz a-law filter/codec with optional squelch figure 1: pin connection - top view tst/se clk sel t shift sys clk t strobe pcm out d gnd c az r shift r strobe pcm in 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 v dd v out out- flt out pdb v in in- in+ c az gnd a gnd v ss MV3506/ 7/8 dg22 advance information
MV3506/7/8 2 ds1 (t1 ) line clock recovery circuitry as there are never more than 15 consecutive zeros. an additional feature of the MV3506/7 is a special circuit to eliminate any transmitted idle channel noise during quiet periods. when the input of these chips is-such that for 250ms the only code words generated were +0, -0, +1 or -1, the output word will be a +0. the steady +0 state prevents alternating sign bits or lsb from toggling and thus results in a quieter signal at the decoder. upon detection of a different value, the output resumes normal operation resetting the 250ms timer. this feature is a form of idle channel noise ?quelch?or ?rosstalk suppression? it is of particular importance in the MV3506 a- law version because the a-law transfer characteristic has ?id-riser?bias which enhances low level signals from crosstalk. receive section a receive shift clock, variable between the frequencies of 64khz and 2.048mhz clocks the pcm data into the input buffer register once every sampling period (see figs.5 and 6). a charge proportional to the received pcm data word appears on the decoder capacitor array of the digital to analog converter. a sample and hold circuit, initialised to zro by a narrow pulse at the beginning of each sampling period, integrates the charge and holds it for the rest of the sampling period . the receive filter, consisting of a switched-capacitor fihhorder low-pass filter clocked at 256khz, smooths the sampled and held signal. it also performs the loss equalisation to compensate for the sin(x)/x distortion due to the sampling. the filter output (flt out pin) is available for driving electronic hybrids directly as long as the impedance is greater than 20k w . when used in this fashion the low impedance output amp can be switched off for a considerable saving in power consumption. when it is required to drive a 600 w load the output amp allows gain trimming as well as impedance matching. functional descrlption fig.2 shows the simplified block diagram of the devices. they contain independent circuitry for processing transmit and receive signals. switched capacitor filters provide the necessary bandwidth limiting of voice signals in both directions. circuitry for coding and decoding operates on the principle of successive approximation, using charge redistribution in a binary weighted capacitor array to define segments and a resistor chain to define steps. transmit section input analog signals first enter the chip at the uncommitted op.amp. terminals (in+ and in- pins). this allows for the gain in the system to be trimmed. from the v in pin the signal enters a second-order analog anti-aliasing filter. this filter eliminates the need for any off-chip filtering as it provides attenuation of 34db (typically) at 256khz and 44db (typically) at 512khz. the signal next enters the transmit filter, which is a fifth order low-pass filter clocked at 256khz, followed by a third order high-pass filter clocked at 64khz. the resulting bandpass characteristics meet the ccitt specifications g.711, g.712 and g.733. some representative attenuations are better than 26db from 0 to 60hz and better than 35db from 4.6khz to 100khz. the output of the transmit filter is sampled at the analog to digital encoder by a capacitor array at the sampling rate of 8khz. the successive approximation conversion process requires about 72 m sec. the 8-bit pcm data is clocked out by the transmit shift clock which can vary from 64khz to 2.048mhz in 8khz steps (see figs. 3 and 4). a switched capacitor dual-speed, autozero loop using a small non-critical external capacitor (0.1 m f) provides dc offset cancellation by integrating the sign bit of the pcm data and feeding it back to the noninverting input of the comparator. included in the circuitry of the mv3507 is ?ll zero?code suppression so that negative input signal values between decision values numbers 127 and 128 are encoded as 00000010. this prevents loss of repeater synchronisation by v in v out pdb tst/se caz c az gnd t strobe t shift pcm out ta/bsel a in b in r strobe r shift pcm in ra/b sel a out b out v dd d gnd v ss a gnd flt out out- sys clk clk sel in- in+ anti-aliasing filter transmit filter a to d encoder transmit interface receive interface d to a decoder receive filter clock generator + - + - 21(25) 4(5) 2(3) 16(20) 15(19) 17(21) 18(22) 1(28) 8(11) 14(18) 5(6) 3(4) 6(7) (26) (2) (1) 10(14) 9(13) 11(15) (12) (10) (9) 22(27) 7(8) 12(16) 13(17) 19(23) 20(24) figure 2: functional block diagram (pin numbers for the mv3507a are in brackets)
MV3506/7/8 3 sys clk t strobe figure 3: transmit strobe alignment timing requirements the internal design of the devices paid careful attention to the timing requirements of various systems. in north america, central office and channel bank designs often follow the american telephone and telegraph company? t1 (ds1) carrier pcm format to multiplex 24 voice channels at a data rate of 1.544m b/s. pabx designs, on the other hand, may use their own multiplexing formats with different data rates. nevertheless, in digital telephone designs, codecs may be used in a non-multiplexed form with data rate as low as 64kbit/ s. the m -law codecs fulfil these requirements. in europe, telephone exchange and channel bank designs often follow the ccitt carrier pcm format to multiplex 30 telephony channels at a data rate of 2.048mbit/s. the a-law codecs are designed for this market and will also handle pabx and digital telephone applications. the timing format chosen for the devices allows operation in both multiplexed or non-multiplexed form with data rates variable from 64kbit/s to 2.048mbit/s. use of separate internal clocks for filters and for shifting of pcm input/output data allows for this variation. the devices do not require that the 8khz transmit and receive sampling strobes be exactly 8 bit periods wide. the device has an internal bit counter that counts the number of data bits shifted. it is reset on the leading ( +ve) edges of the strobe, forcing the pcm output into its high impedance state after the 8th bit is shifted out. this allows the width of the strobe signal to vary as long as its repetition rate is 8khz and the transmit and receive shift clocks are synchronised to it. system clock the basic timing is provided by the system clock which is divided down internally to provide the various filter clocks and the timing for the conversions. the transmit and receive strobes and clocks must be locked to this clock so that the pcm data matches the sample rates. r shift r strobe pcm in 1234 5678 figure 6: receive alignment sys clk r strobe figure 5: receive strobe alignment t shift t strobe 1234 5678 pcm out figure 4: transmit alignment
MV3506/7/8 4 pin descriptions symbol pin no. . pin name and description 3506/7/8 tst/se 1 test/squelch enable (intemal connection/digital input). this pin is an internal test connection on the MV3506, mv3507 and it is the squelch enable input on the mv3508. on the MV3506/7 it should be left unconnected or connected to the a gnd pin via a capacitor for normal operation. on the mv3508 it should be tied high to enable the squelch feature and it should be left unconnected otherwise. clk sel 2 clock select (three level input). this pin selects the proper divide ratios for a 256khz, 1.544mhz or 2.048mhz system clock. the pin is tied to v dd (+5v) for 2.048mhz operation, to d gnd (0v) for 256khz operation, and to v ss (-5v) for 1.544mhz operation. t shift 3 transmit shift clock (digital input). this ttl compatible input shifts pcm data out of the coder on the positive going edges after receiving a positive edge on the t strobe input. the clocking rate can vary from 64khz to 2.048mhz. sys clk 4 system clock (digital input). this pin is a ttl compatible input for either a 256khz, 1.544mhz or a 2.048mhz clock that is divided down to provide the filter clocks. the status of the clk sel pin must correspond to the provided clock frequency. t strobe 5 transmit strobe (digital input with pull-up). this ttl compatible pulse input (typically 8khz) is used for analog sampling and initiating the pcm output from the coder. it must be synchronised with the t shift and sys clk clocks with its positive going edges occurring after the falling edges of these clocks. the width of this signal is not critical. an internal bit counter generates the necessary timing for pcm output. pcm out 6 pcm out (pull-down output). this is a ls ttl compatible open-drain output. it is active only during transmission of pcm output for 8-bit periods of the t shift clock signal following positive edge on the t strobe input. data is clocked out by the positive edge on the t shift clock into one 510 w pull-up per system plus 2 ls ttl inputs. d gnd 7 digital ground (power input). 0v. caz 8 auto zero capacitor (reterence node) . a capacitor of 0.1 m f ( 20%) should be connected between this pin and caz gnd for coder auto zero operation. the sign bit of the pcm data is integrated and fed back to the comparator for dc offset cancellation. r shift 9 receive shift clock (digital input). this ttl compatible input shifts pcm data into the decoder on the negative going edges after receiving a positive edge on the r strobe input. the clocking rate can vary from 64khz to 2.048mhz. r strobe 10 receive strobe (digital input with pull-up). this ttl compatible pulse input (typically 8khz) initiates clocking of pcm input data into the decoder. it must be synchronised with the r shift and sys clk clocks with its positive going edges occurring after the falling edges of these clocks. the width of the signal is not critical. an internal bit counter generates necessary timing for pcm input. pcm in 11 pcm in (digital input). this is a ttl compatible input for supplying pcm input data to the decoder. data is clocked in by the negative edge of the r shift clock. v ss 12 negative supply (power input) . -5v. a gnd 13 analog ground (reference node). this is the ground reference node for analog signals.
MV3506/7/8 5 pin descriptions (continued) symbol pin no. . pin name and description 3506/7/8 c az gnd 14 auto zero capacitor ground (reterence node). a capacitor of 0.1 m f ( 20%) should be connected between this pin and c az for coder auto zero operation. the sign bit of the pcm data is integrated and fed back to the comparator for dc offset cancellation. in +, in- 15,16 in positive and negative (analog voltage inputs). these are the differential inputs of a high input impedance op amp whose output is connected to the v in pin. these three pins allow the user complete control over the input stage so that it can be connected as a fixed gain amplifier, as an amplifier with adjustable gain, or as a . differential input amplifier the adjustable gain configuration will facilitate calibration of the transmit channel. v in 17 input voltage (analog high-impedance voltage output). this is the output of a high input impedance op amp whose differential inputs are the in + and in- pins. this node feeds the rest of the analog input section. pdb 18 power down bar (digital input with pull-up). this ttl compatible input, when held low, puts the chip into the powered down mode regardless of strobes. the chip will also power down if the strobes stop. the strobes can be high, low or floating, but as long as they are static, the powered down mode is in effect. flt out 19 filter out (analog high-impedance voltage output). this is the output of the low pass filter which represents the recreated analog signal from the received pcm data words. the filter sample frequency of 256khz is down 37db at this point. this is a high impedance output which can be used by itself or connected to the output amplifier stage which has a low output impedance. it should not be loaded by less than 20k w . out- 20 out negative (analog voltage input). this is the inverting input of the uncommitted output amplifier stage, which has its non-inverting input connected internally to ground and its output connected to vout. the signal at the flt out pin can be connected to this pin to realise a low output impedance with unity, increased or reduced gain. this allows easy calibration of the receive channel. if out- is connected directly to vss then the op amp will be powered down, reducing power consumption by 10mw typically. v out 21 output voltage (analog voltage output). this is the output of the uncommitted output amplifier stage, which has its inverting input connected to the out- pin and its non-inverting input connected internally to ground. the signal at the flt out pin can be connected to out- to realise a low output impedance with unity, increased or reduced gain. this allows easy calibration of the receive channel. the v out pin has the capability of driving 0dbm into a 600 w load (see fig.4) . v dd 22 positive supply (power input). 5v.
MV3506/7/8 6 electrical characteristics test conditions - voltages are with respect to digital ground (v dgnd ) characteristic symbol value units min. typ.(1) max. digital supply voltage v dd 4.75 5 5.25 v negative supply voltage v ss -5.25 -5 -4.75 v analog ground voltage v agnd -0.1 0 0.1 v ambient temperature v amb 070 c input low voltage - digital inputs v il 0 0.4 0.8 v input high voltage - digital inputs v ih 2.0 2.4 v dd v system clock frequency clk sel tied to v dd f s 2047.90 2048 2048.10 khz clk sel tied to d gnd 255.99 256 256.01 clk sel tied to v ss 1549.92 1544 1544.08 capacitive loading - digital outputs c ld 0 100 pf pull-up resistance for pcm out pin r pu 510 w analog input voltage v ia v agnd ?.1 v agnd +3.1 v capacitive loading - analog outputs c la 50 pf resistive loading - v out pin r vout 1200 w resistive loading - v in pin r vin 10 k w resistive loading - flt out pin r rltout 20 k w power supply requirements - v dd = 5v, v ss = -5v characteristic symbol value units conditions min. typ. max. power dissipation - normal p in 80 110 mw unloaded power dissipation - without p wa 70 mw unloaded output amp. power dissipation - standby p s 10 20 mw unloaded static characteristics - voltages are with respect to digital ground (v dgnd ) characteristic symbol value units conditions min. typ. (1) max. pin capacitance c pin 715pf input leakage current i il 1 m a 0 < v < v dd input source current - inputs i is 600 m a 0 < v < v dd with pull-ups output high voltage v oh 2.4 vdd v i oh (source) = 40 m a output low voltage v ol 0 0.4 v l ol (sink) = 1.6ma output leakage current l ol 10 m a 0 < v < v dd analog input resistance r ia 100 k w analog output voltage v oa v agnd v agnd v -3.1 +3.1
MV3506/7/8 7 digital switching characteristics - system clock (see fig.7) value characteristic symbol min. typ. max. units conditions system clock rise time t sr 50 ns system clock high period t sh 0.4/fs 0.6/fs s system clock fall time t sf 50 ns system clock low period t sl 0.4/fs 0.6/fs s digital switching characteristics - receive strobe and clock (see figs. 8 and 9) characteristic symbol value units conditions min. typ.(1 ) max. receive strobe frequency f rs 7.99996 8.00004 khz phase-locked with system clock receive strobe falling set-up time t rsfs 120 ns receive strobe early jitter t rsej 200 ns receive strobe late jitter t rslj 100 ns receive strobe falling hold time t rsfh 220 ns receive clock frequency f rc 63.9997 2048.01 khz phase-locked with receive strobe receive clock rise time t rcr 100 ns receive clock high period t rch 0.4/f rc 0.6/f rc s receive clock fall time t rcf 100 ns receive clock low period t rcl 0.4/f rc 0.6/f rc s receive clock early jitter t rcej 200 ns receive clock late jitter t rslj 100 ns 2.0v 0.8v sys clk t sr t sf t sh t sl figure 7: timing - system clock
MV3506/7/8 8 2.0v 0.8v sys clk t rfs 2.0v 0.8v r strobe t rsej t rslj t rsfh figure 8: timing - receive strobe 2.0v 0.8v r shift t rch r strobe t rcej t rclj 2.0v 0.8v t rcl t rcl t rcr figure 9: timing - receive clock 2.0v 0.8v r strobe t pis r shift 2.0v 0.8v t pih t pis t pih pcm in 2.0v 0.8v bit 1 bit n figure 10: timing - receive data digital switching characteristics - receive data (see fig.10) value characteristic symbol min. typ. ( 1 ) max. units conditions pcm input set-up time t pls 60 ns pcm input hold time t plh 60 ns
MV3506/7/8 9 digital switching characteristics - transmit strobe and clock (see figs.11 and 12) characteristic symbol value units conditions min. typ. ( 1 ) max. transmit strobe frequency f ts 7.99996 8 8.00004 khz phase-locked with system clock transmit strobe falling t tsfs 120 ns set-up time transmit strobe early jitter t tsej 200 ns transmit strobe late jitter t tslj 100 ns transmit strobe falling hold time t tsfh 220 ns transmit clock frequency f tc 63.9997 2048.01 khz phase-locked with transmit strobe transmit clock rise time t tcr 100 ns transmit clock high period t tch 0.4/f tc 0.6/ tc s transmit clock fall time t tcf 100 ns transmit clock low period t tcl 0.4/f tc 0.6/f tc s transmit clock early jitter t tcej 200 ns transmit clock late jitter t tclj 100 ns 2.0v 0.8v sys clk t tsfs 2.0v 0.8v t strobe t tsej t tslj t tsfh figure 11: timing - receive strobe 2.0v 0.8v t shift t tch t strobe t tcej t tclj 2.0v 0.8v t tcl t tcl t tcr figure 12: timing - receive clock
MV3506/7/8 10 digital switching characteristics - transmit data (see fig.13) value characteristic symbol min typ (1) | max units conditions pcm output holt time t poh 050 ns pcm output delay t pod 100 150 ns 2.0v 0.8v t strobe t pod t shift 2.0v 0.8v pcm out 2.0v 0.8v bit 1 bits 2 to 7 bit 8 t pod t pod t pod t poh t poh t poh t poh figure 13: timing - transmit data analog channel characteristics - filter delays value characteristic symbol min typ.(1) max. units conditions transmit filter delay t tfd 182 m s 1khz receive filter delay t rfd 110 m s 1khz analog channel characteristics - a-law characteristic symbol value units conditions min. typ. (1) max. 0dbm0 level (see note 2) 0dbm0 5.3 5.8 6.3 dbm 5v, 25 c variation in 0dbm0 level d 0dbm0 -0.3 0 0.3 db over test conditions weighted idle channel noise icn w -85 -73 dbm0p ccitt g.712, ?.1 (see note 3) single frequency icn sf -60 dbm0 ccitt g.712, ?.2 idle channel noise weighted receive icn wr -78 dbm0p ccitt g.712, ?.3 idle channel noise spurious out-band noise n sob -30 dbm0 ccitt g.712, ?.1 spurious in-band noise n sib -40 dbm0 ccitt g.712, ?0 two tone interdemodulation imd 2t -35 dbm0 ccitt g.712, ?.1 tone + power inter- imd tp -49 dbm0 ccitt g.712, ?.2 demodulation crosstalk attenuation between ax 75 80 db ccitt g.712, ?2 v in and v out
MV3506/7/8 11 analog channel characteristics - m -law characteristic symbol value units conditions mln. typ. (1) max. 0dbm0 level (see note 2) 0dbm0 5.3 5.8 6.3 dbm 5v, 25 c variation in 0dbm0 level d dbm0 -0.3 0 0.3 db over test conditions weighted idle channel noise icn w 5 17 dbrnc0 at&t d3 (see note 3) single frequency icn sf -60 dbm0 at&t d3 idle channel noise weighted receive icn wr 15 dbrnc0 at&t d3 idle channel noise spurious out-band noise n sob -28 dbm0 at&t d3 spurious in-band noise n sib -40 dbm0 at&t d3 two tone interdemodulation imd 2t -35 dbm0 at&t d3 tone + power inter- imd tp -49 dbm0 at&t d3 demodulation crosstalk attenuation between ax 75 80 db at&t d3 v in and v out figure 14: simple application circuit notes 1 . typical figures are for design aid only they are not guaranteed and not subject to production testing 2. the typical 0dbm0 level of 58dbm corresponds to an rms voltage of 1.51v and a maximum coding level of 3.1v 3. the maximum value reduces to -68dbm0p without squelch (mv3508 with tst/se pin unconnected) absolute maximum ratings exceeding these ratings may cause permanent damage. functional operation under these conditions is not implied. positive supply voltage v dd -0.5v to +6.0v analog ground v agnd -0.1v to +0.1v negative supply voltage v ss -6.0v to +0 5v storage temperature ts -65 c to +150 c voltage at digital or analog pins v p v ss -0.3v to v dd +0.3v package power dissipation p 1000mw 0.1 m 814 5 3 6 10 9 11 2 4 5v 8khz strobe 2048khz clock pcm output pcm input digital ground analog ground -5v 1 7 13 12 21 20 19 15 16 17 v out v in in- in in+ flt out out- a gnd v ss d gnd tst/se sys clk clk sel pcm in r shift r strobe pcm out t shift t strobe gaz gnd caz pdb v dd 18 22 analog input analog output MV3506/7/8
MV3506/7/8 12 headquarters operations gec plessey semiconductors cheney manor, swindon, wiltshire sn2 2qw, united kingdom. tel: (0793) 518000 fax: (0793) 518411 gec plessey semiconductors p.o.box 660017, 1500 green hills road, scotts valley, california 95067-0017, united states of america. tel (408) 438 2900 fax: (408) 438 5576 customer service centres france & benelux les ulis cedex tel: (1) 64 46 23 45 fax: (1) 64 46 06 07 germany munich tel: (089) 3609 06-0 fax : (089) 3609 06-55 italy milan tel: (02) 66040867 fax: (02) 66040993 japan tokyo tel: (3) 5276-5501 fax: (3) 5276-5510 north america integrated circuits and microwave products, scotts valley, usa tel (408) 438 2900 fax: (408) 438 7023. hybrid products, farmingdale, usa tel (516) 293 8686 fax: (516) 293 0061. south east asia singapore tel: 2919291 fax: 2916455 sweden johanneshov tel: 46 8 702 97 70 fax: 46 8 640 47 36 uk, eire, denmark, finland & norway swindon tel: (0793) 518510 fax : (0793) 518582 these are supported by agents and distributors in major countries world-wide. gec plessey semiconductors 1993 publication no. ds 3133 issue no. 2.1 september 1993 this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regard ing the capability, performance or suitability of any product or service. the company reserves the right to alter without prior knowledge the specification, design or price of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, w hich are available on request.
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